Polysilicon-Based Synaptic Transistor and Array Structure for Short/Long-Term Memory.

In this paper, we proposed and fabricated a polysilicon-based four-terminal synaptic transistor. The device has an asymmetric dual-gate structure. The top gate, which uses a thin SiO₂ layer as the gate dielectric, is the input terminal of the synaptic transistor, which receives spikes from pre-synaptic neurons. Meanwhile, a nitride trapping layer was inserted between the channel and the bottom gate to serve as a non-volatile memory. The bottom gate is the node that receives the post-neuron feedback signals and adjusts the synaptic weight. With this double-gate structure, the proposed artificial synapse can perform short-/long-term memory operations. In addition to the basic unit cell characteristics, a highly integrated synapse array structure is also proposed. In our array structure, the top gate is tied in the word-line direction to accept the input signal. Drain contacts are also tied in the same direction. With regard to bit-line direction, the source terminals are tied to carry post-synaptic signals and the bottom gate line receives feedback signals from the post-synaptic neurons.

Citation

Myung-Hyun Baek, Taejin Jang, Min-Woo Kwon, Sungmin Hwang, Suhyeon Kim, Byung-Gook Park. Polysilicon-Based Synaptic Transistor and Array Structure for Short/Long-Term Memory. Journal of nanoscience and nanotechnology. 2019 Oct 01;19(10):6066-6069

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PMID: 31026909

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